1. Field of the Invention
This invention relates to a computer system and more particularly to the interconnection of a power management unit (PMU) to a clock control unit having multiple phase-locked loops for programmably clocking various clocked circuits according to an operational state of the PMU.
2. Description of the Relevant Art
Manufacturers have demonstrated an ability to place an increasing amount of circuitry upon a single monolithic semiconductor substrate or "chip". The advent of portable data processing systems, herein referred to as personal information devices ("PIDs"), has lead a push toward placing an even greater amount of circuitry on a single chip. As defined herein, PIDs include any portable CPU-based system, such as pocket personal computers (PCs), digital assistants (test units, meters, etc.), "smart" phones, and electronic calendars, organizers, booklets, etc.
Functional demands of modern PIDs typically require that they be data-intensive, view-intensive and/or voice-intensive. For example, a pocket personal computer may be called upon to perform extensive data calculations involving data-intensive functions. Additionally, a pocket personal computer may also require, for example, a detailed, object-oriented display requiring view-intensive functions. On the other hand, a smart phone may require voice-intensive functions, and not necessarily view and/or data-intensive functions. Therefore, an integrated processor system which is intended for use within of a wide range of PID applications must include the necessary subsystems to accommodate all three types of functionality.
In addition to the above technical features, an integrated processor for PIDs must also operate at low power within a small package outline, and should preferably be available at a low cost. Unfortunately, an effort to lower cost by reducing, for example, the pin-count of the integrated processor may require the elimination of certain desirable subsystems of the integrated processor, thus limiting functionality and/or performance. Power consumption may similarly be adversely affected by the incorporation of certain subsystems or by the requirement of a variety of differing crystal oscillator circuits to clock the various subsystems. Integrated processors for PIDs which achieve acceptable performance capabilities while maintaining wide versatility, small size, low power consumption, and low cost are largely unavailable.
A high performance, versatile integrated processor is therefore desirable which is adaptable to data-intensive, view-intensive and/or voice-intensive PID applications. Such an integrated processor should additionally be characterized by small size, low power consumption, and low cost.